43 results found in 26 ms
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Title: TEGRA MULTICORE SW ARCHITECT at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Time Stamp: Wed Dec 21 05:17:10 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215605
Title: SYSTEM PRODUCT ENGINEER at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Time Stamp: Wed Dec 21 04:07:54 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215704
Title: GPU DEVELOPMENT TOOLS ARCHITECT at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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silicon
stage
simulation
Perl
analysis
graphics
OpenGL
strength
system simulation
C++
GPU
engineers
Direct3D
core
studies
Architecture
Graphics
frameworks
schedules
STL
C
dynamic
debugging
critical
programming
Cuda
Science
scripting
world
proprietary
modeling
visualization
feedback
Computer Science
CUDA
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Time Stamp: Wed Dec 21 00:30:37 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215869
Title: FINANCIAL REPORTING ANALYST at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Time Stamp: Tue Dec 20 15:38:48 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215924
Title: MOBILE WEB GRAPHICS SOFTWARE MANAGER at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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engineering
analysis
Adobe
Flash
rendering
OpenGL
engineers
MOBILE
codecs
Android
driving
technical leadership
Ideal
benchmarking
HTML
release
mobile
rest
performance analysis
Linux
WEB
platforms
C
Travel
software engineering
mobile platforms
HTML5
hiring
programming
web
edge
improving
world
GRAPHICS SOFTWARE
career development
national
2D
GRAPHICS
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Time Stamp: Tue Dec 20 16:36:32 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215656
Title: SOFTWARE TEST AUTOMATION ENGINEER, DIRECTX at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Time Stamp: Tue Dec 20 18:18:19 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215667
Title: SENIOR ASIC TIMING ENGINEER at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Perl
analysis
routing
ECO
rules
BIST
physical design
electrical
boundary
physical
timing
TIMING
power
capture
sizing
DFT
Analysis
techniques
Electrical
hardware
Tcl
checking
ASIC
timing closure
automation
scripting
improving
closing
r
modeling
process
convergence
Engineering
optimization
cell
Timing
EDA
closure
language
aspect
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Time Stamp: Wed Dec 21 00:30:15 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215700
Title: AUTODESK ALLIANCE MANAGER at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Moldflow
engineering
analysis
product strategy
alignment
revenue
graphics
messaging
rendering
units
potential
channel
GPU
growth
business metrics
Manufacturing
Culture
ISV
MBA
metrics
editing
Automotive
AEC
mobile
Video
Modeling
compositing
serving
business growth
Travel
hardware
Content
OEM
clear
AUTODESK
Content Creation
world
PhysX
modeling
independent
business reviews
groups
3D
providers
drive
hosting
Broadcast
Animation
Competitive analysis
Autodesk
content
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Time Stamp: Tue Dec 20 23:38:07 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215722
Title: SENIOR ASIC TIMING ENGINEER at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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analysis
Perl
formal verification
routing
rules
ECOs
physical design
electrical
physical
timing
TIMING
sizing
Analysis
techniques
Electrical
Tcl
ASIC
timing closure
automation
scripting
improving
closing
improvement
modeling
process
static timing analysis
convergence
Engineering
optimization
cell
Timing
EDA
closure
quality
language
aspect
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Time Stamp: Tue Dec 20 22:51:25 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215832
Title: PRODUCT FAILURE ANALYSIS ENGINEER at NVIDIA in US, CA, Santa Clara - Job | LinkedIn
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Time Stamp: Wed Dec 21 03:35:06 CET 2011
URL: http://www.linkedin.com/jobs?viewJob=&jobId=2215865